In the transmission of data between a memory and a CPU, etc., impedance matching in the transmission line is required in cases where transmission is performed at high speeds. An interface of a memory compliant with DDR2 (Double Data Rate 2) established by the JEDEC (Joint Electron Device Engineering Council) is required to have a termination circuit on the controller side of the memory. If we assume that the impedance of the transmission line is 75Ω in this case, the terminating resistance value will be 75Ω if the controller and memory are connected 1:1. On the other hand, if controller and memory are connected 1:2, it is required to so arrange it that the terminating resistance value can be changed over to 150Ω. Furthermore, the termination circuit is required to have a Thevenin termination.
A termination circuit forms a Thevenin termination by providing a resistance unit between the transmission line and power supply line and between the transmission line and ground line so as to achieve impedance matching with the transmission line, and the termination circuit is provided in association with input/output buffer(s). Further, in order to achieve impedance matching with a transmission line, the terminating resistance value is set to a suitable value in accordance with conditions. As such as example, Patent Document 1 discloses a termination circuit having a resistance unit formed by connecting a pair of a P-channel MOS transistor and an N-channel MOS transistor in parallel, wherein a Thevenin termination is formed by providing a resistance unit between the transmission line and a power supply line and between the transmission line and a ground line. In accordance with this termination circuit, it is possible to improve the matching characteristic of a transmission line using transistors as terminating resistors.
As related art, Patent Document 2 discloses a semiconductor integrated circuit device in which an output circuit has a plurality of parallel-configured output MOSFETs, output impedance is adjusted by a first control means which selects a number of the plurality of output MOSFETs that are turned on, and slew rate is adjusted by a second control means by adjusting drive signals of the output MOSFETs which are turned on. In accordance with this semiconductor integrated circuit device, it is possible to set adjustment of impedance and adjustment of slew rate mutually independently, thereby simplifying the configuration of the adjustment circuitry.
[Patent Document 1] Japanese Patent Kokai Publication JP-2006-42136A
[Patent Document 2] Japanese Patent Kokai Publication JP-2004-327602A
The entire disclosures in the above-mentioned Patent Documents are incorporated herein by reference thereto.
The analysis set forth below is given in the present invention.